In this project, we utilized the Sentaurus TCAD tool to simulate deep submicron NMOS transistors, focusing on the intricate relationship between doping concentrations and device behavior. By designing 45nm gate length NMOS transistors, we systematically tested and selected optimal halo and source/drain extension doping concentrations to mitigate short-channel effects.
Our objective was to refine the design to meet specific on and off current thresholds for different applied voltages, observing performance in both linear and saturation regimes. Key terms such as threshold voltage and DIBL were explored, and our results were benchmarked against TSMC’s 65nm CMOS technology, providing valuable insights into transistor performance and optimization.
If you are interested in learning more about this project, a comprehensive report is available below.